Synthesis of pipelined DSP accelerators with dynamic scheduling

  • Authors:

  • Patrick Schaumont;Bart Vanthournout;Ivo Bolsens;Hugo J. De Man

  • Affiliations:

  • Interuniversity Micro-Electronics Center, Leuven, Belgium;Interuniversity Micro-Electronics Center, Leuven, Belgium;Interuniversity Micro-Electronics Center, Leuven, Belgium;Interuniversity Micro-Electronics Center and Katholieke Univ. Leuven, Leuven, Belgium

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1997

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Abstract

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis is put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology is illustrated by means of an image encoding filter bank.