High-level algorithm and architecture transformations for DSP synthesis

A methodology for guided behavioral-level optimization

DAC '98 Proceedings of the 35th annual Design Automation Conference

System-Level Data-Flow Transformation Exploration andPower-Area Trade-offs Demonstrated on Video Codecs

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design

Power optimization using divide-and-conquer techniques for minimization of the number of operations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Architectural Synthesis of Computational Engines for Subband Adaptive Filtering

Journal of VLSI Signal Processing Systems

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Journal of VLSI Signal Processing Systems

An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits

IEEE Transactions on Computers

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Layout-aware synthesis of arithmetic circuits

Proceedings of the 39th annual Design Automation Conference

Performance-Scalable Array Architectures for Modular Multiplication

Journal of VLSI Signal Processing Systems

An integrated approach to timing-driven synthesis and placement of arithmetic circuits

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Verification method of dataflow algorithms in high-level synthesis

Journal of Systems and Software