VLSI array processors
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
IEEE Transactions on Computers - Special issue on computer arithmetic
Partitioning of processor arrays: a piecewise regular approach
Integration, the VLSI Journal - Special issue on algorithms and architectures
High-level algorithm and architecture transformations for DSP synthesis
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
IEEE Transactions on Computers
VLSI array algorithms and architectures for RSA modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two systolic architectures for modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
IEEE Transactions on Computers
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Simplifying Quotient Determination in High-Radix Modular Multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.