Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
RSA cryptosystem design based on the Chinese remainder theorem
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Architectural support for fast symmetric-key cryptography
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
A Systolic, High Speed Architecture for an RSA Cryptosystem
Journal of VLSI Signal Processing Systems
A Novel Systolic Architecture for Efficient RSA Implementation
PKC '01 Proceedings of the 4th International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
Hardware architectures for public key cryptography
Integration, the VLSI Journal
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Design of a scalable RSA and ECC crypto-processor
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Journal of Supercomputing
Power-Aware scheduling for parallel security processors with analytical models
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
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We revise Montgomery's algorithm such that modular multiplication can be executed two times faster. Each iteration in our algorithm requires only one addition, while that in Montgomery's requires two additions. We then propose a cellular array to implement modular exponentiation for the Rivest-Shamir-Adleman cryptosystem. It has approximately 2n cells, where n is the word length. The cell contains one full-adder and some controlling logic. The time to calculate a modular exponentiation is about 2n/sup 2/ clock cycles. The proposed architecture has a data rate of 100 kb/s for 512-b words and a 100 MHz clock.