Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
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A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm. The circuit yields low hardware complexity and permits high-speed operation with 100% efficiency.