Methods and applications of error-free computation
Methods and applications of error-free computation
An algorithm for exact division
Journal of Symbolic Computation
Systolic Modular Multiplication
IEEE Transactions on Computers
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
RSA cryptosystem design based on the Chinese remainder theorem
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
A Systolic, High Speed Architecture for an RSA Cryptosystem
Journal of VLSI Signal Processing Systems
Montgomery in Practice: How to Do It More Efficiently in Hardware
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Novel Systolic Architecture for Efficient RSA Implementation
PKC '01 Proceedings of the 4th International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Data Integrity in Hardware for Modular Arithmetic
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Fast modular exponentiation of large numbers with large exponents
Journal of Systems Architecture: the EUROMICRO Journal
Hardware architectures for public key cryptography
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
An 830mW, 586kbps 1024-bit RSA chip design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
An area-efficient bit-serial integer and GF(2n) multiplier
Microelectronic Engineering
Scalable hardware implementing high-radix Montgomery multiplication algorithm
Journal of Systems Architecture: the EUROMICRO Journal
A real-time systolic integer multiplier
Integration, the VLSI Journal
High-Speed RSA crypto-processor with radix-4 modular multiplication and chinese remainder theorem
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
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A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only upper bound [n]/2 cells are needed for a full n by n multiply. A module-multiplier is then developed by incorporating a Montgomery type of module-reduction. Two such multipliers interconnect to form a purely systolic module exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus.