A Systolic, High Speed Architecture for an RSA Cryptosystem

Authors:
K. Z. Pekmestzi;N. K. Moshopoulos
Affiliations:
Electrical and Computer Engineering Department, National Technical University of Athens, Heroon Polytehneiou 9, 15773 Zographou, Athens, Greece;Electrical and Computer Engineering Department, National Technical University of Athens, Heroon Polytehneiou 9, 15773 Zographou, Athens, Greece
Venue:
Journal of VLSI Signal Processing Systems
Year:
2002

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Abstract

An architecture based on the RSA public key cryptography algorithm is presented. The circuit includes two components, one for modular squaring and one for modular multiplication. Each component is based on the Montgomery algorithm and implements the modular operations using two modified serial-parallel multipliers. A full modular exponentiation is completed every n(n + 3) clock cycles. All circuits are systolic, operate with 100% efficiency and their maximum combinational delay is equal to one gated Full-Adder. Thus, high-speed performance is achieved while the low cell hardware complexity enables an efficient VLSI implementation.