A Signed Bit-Sequential Multiplier
IEEE Transactions on Computers
Comments, on 'A Signed Bit-Sequential Multiplier' by T. Rhyne and N.R. Strader II
IEEE Transactions on Computers
On Serial-Input Multipliers for Two's Complement Numbers
IEEE Transactions on Computers
A Systolic, High Speed Architecture for an RSA Cryptosystem
Journal of VLSI Signal Processing Systems
A core generator for arithmetic cores and testing structures with a network interface
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 14.98 |
Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries.