A core generator for arithmetic cores and testing structures with a network interface

Authors:
D. Bakalis;K. D. Adaos;D. Lymperopoulos;M. Bellos;H. T. Vergos;G. Ph. Alexiou;D. Nikolos
Affiliations:
Computer Engineering and Informatics Department, University of Patras, Patras, Greece and Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece and Research Academic Computer Technology Institute, Patras, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece and Research Academic Computer Technology Institute, Patras, Greece
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2006

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Abstract

We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication, division, squaring, square rooting and shifting, and (b) several testing structures that can be used as test pattern generators and test response compactors. Interaction with the user is made through a network interface. Since the end user is presented with a variety of unencrypted structural cores, each one describing an architecture with its own area, delay and power characteristics, he can choose the one that best fits his specific needs which he can further optimize or customize. Therefore, designs utilizing these cores arc completed in less time and with less effort.