Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
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DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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EDTC '95 Proceedings of the 1995 European conference on Design and Test
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VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
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Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
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Journal of Electronic Testing: Theory and Applications
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GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
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Journal of Electronic Testing: Theory and Applications
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
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Journal of Systems Architecture: the EUROMICRO Journal
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Configurations of adders, subtracters, or arithmetic logic units andregisters, which are available in many data paths, can be utilized togenerate patterns and to compact test responses. This paper analyzesthe pattern sequences generated by configurations with differenttypes of adders and subtracters. For many different seeds andconstant input values, these pattern generators can produce asequence of all possible patterns. Moreover, k-bit patterngenerators that take into account the overflow or underflow bit cangenerate bit sequences that all have period 2^k-1. Thus, theperiodicity of these pattern generators is the same as that of ak-bit linear feedback shift register with a primitivecharacteristic polynomial. Experimental results show that theproduced pattern sequences achieve similar fault coverage aspseudorandom sequences and require about the same testlength. Compared to the well-known self-test methods that insert testregisters, the approach using available arithmetic units saves theadditional gates that are needed to implement test registers, and itavoids performance degradation due to additional delays.