Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital signal processing in VLSI
Digital signal processing in VLSI
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Recursive Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers
An efficient built-in self test method for robust path delay fault testing
Journal of Electronic Testing: Theory and Applications
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Digital Design
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An algebraic method for delay fault testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On Using Efficient Test Sequences for BIST
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Built-in test for CMOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
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The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.