Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage
IEEE Transactions on Computers - Fault-Tolerant Computing
Linear Feedback Shift Register Design Using Cyclic Codes
IEEE Transactions on Computers
Locally exhaustive testing of combinational circuits using linear logic circuits
Journal of Information Processing
Exhaustive Test Pattern Generation Using Cyclic Codes
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators that can be easily adopted in a scan-based built-in self-test environment.