Recursive Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
Novel Test Pattern Generators for Pseudoexhaustive Testing
IEEE Transactions on Computers
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
An Effective BIST Scheme for Booth Multipliers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata
ATS '02 Proceedings of the 11th Asian Test Symposium
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounds on pseudoexhaustive test lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On n-detection test sets and variable n-detection test sets for transition faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n, k)-adjacent bit pseudo-exhaustive test sets, all 2k binary combinations appear to all adjacent k-bit groups of inputs.With recursive pseudoexhaustive generation, all (n, k)-adjacent bit pseudoexhaustive tests are generated for and k ≤ n more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern (n, k)-adjacent bit pseudoexhaustive tests for all k ≤ n. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.