Journal of Electronic Testing: Theory and Applications
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We consider the problem of fault detection in iterative logic arrays (ILA's). This problem has been studied by numerous researchers for many years. The results can be succinctly summarized by stating that one dimensional arrays can be effectively analyzed and significant results obtained while the problems associated with arrays of dimension two or greater appear to be intractable (i.e., NP-complete) for general arbitrary ILA's. However as is the case for many other switching theory problems, general case problems that are intractable, can be readily handled for the special cases defined by functions commonly encountered in practice. We show that arrays of dimension two or greater can be effectively tested for the case when the functions defined by the arrays have inverses. Many specific arithmetic functions satisfy this property. We also show that even for functions which do not satisfy this property, the functional approach simplifies testing problems considerably.