Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Testability of Convergent Tree Circuits
IEEE Transactions on Computers
Testability Properties of Divergent Trees
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
On the design of fast, easily testable ALU's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Regular Structures and Testing: RCC-Adders
AWOC '88 Proceedings of the 3rd Aegean Workshop on Computing: VLSI Algorithms and Architectures
Design of a fast, easily testable ALU
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Properties of the input pattern fault model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
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Cellular Carry Lookahead (CLA) adders are systematically implemented in arithmetic units due to their regular, well-balanced structure. In terms of testability and with respect to the classical Cell Fault Model (CFM), cellular CLA adders have poor testability by construction. Design-for-testability (DFT) modifications for cellular CLA adders have been proposed in the literature providing complete CFM testability making the adders either level-testable or C-testable. These designs impose significant area and performance overheads. In this paper, we propose DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance. Complete CFM testability is achieved without adding any extra inputs to the adder, with very small area and performance overheads, thus providing a practical solution. The proposed DFT scheme requires only 1 extra output and it is not necessary to put the circuit in a special test mode, while the earlier schemes require the addition of 2 extra inputs to set the circuit in test mode. A rigorous proof of the linear-testability of the adder is given and a sufficient linear-sized test set is provided that guarantees 100% CFM fault coverage. Surprisingly, the size of the proposed linear-sized test set is, in most practical cases, comparable or even smaller than a logarithmic-sized test set proposed in the literature.