Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
The Design of a Testable Parallel Multiplier
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Journal of Electronic Testing: Theory and Applications
Testability of Convergent Tree Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
Design of a fast, easily testable ALU
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the generation of area-time optimal testable adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
Power-/Energy Efficient BIST Schemes for Processor Data Paths
IEEE Design & Test
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Testing digital low-pass filters using oscillation-based test
Microprocessors & Microsystems
| Hi-index | 14.99 |
In this paper, an effective Built-In Self-Test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (carry-propagate or carry-save array multiplier or tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with very small hardware overhead equivalent to the hardware overhead of pseudorandom testing.