Digital logic testing and simulation
Digital logic testing and simulation
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Built-In Checking of the Correct Self-Test Signature
IEEE Transactions on Computers
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Built-In Self-Diagnostic Read-Only-Memories
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Programmable BIST Space Compactors
IEEE Transactions on Computers
An Effective Multi-Chip BIST Scheme
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Multichip Module Diagnosis by Product-Code Signatures
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
Testability Features of the AMD-K6 Microprocessor
IEEE Design & Test
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An efficient comparative concurrent Built-In Self-Test technique
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
An Effective BIST Scheme for Arithmetic Logic Un i t s
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testability Features of AMD-K6" Microprocessor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Low-Cost Concurrent BIST Scheme for Increased Dependability
IEEE Transactions on Dependable and Secure Computing
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR.