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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
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VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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ITC '99 Proceedings of the 1999 IEEE International Test Conference
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
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This article describes the testability features and test pattern development methodologies for the AMD-K6 Microprocessor. The embedded Design for Testability (DFT) structures and test strategy provide high quality manufacturing tests.