E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
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Logic Testing of Bridging Faults in CMOS Integrated Circuits
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Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
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Fast and Accurate CMOS Bridging Fault Simulation
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Switch-level bridging fault simulation in the presence of feedbacks
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Detecting bridging faults with stuck-at test sets
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An efficient CMOS bridging fault simulator: with SPICE accuracy
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Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
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Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
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Modeling Feedback Bridging Faults with Non-Zero Resistance
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A bridging fault model where undetectable faults imply logic redundancy
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Detectability of internal bridging faults in scan chains
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Partitioned n-detection test generation
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Robust fault models where undetectable faults imply logic redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This study provides bridging fault simulation dataobtained from the AMD-K6 microprocessor.It shows that:1) high stuck-at fault coverage (99.5%) implies highbridging fault coverage; 2) coverage of a bridging fault byboth wired-AND and wired-OR behavior does notguarantee detection of that fault when compared against amore accurate (transistor-level simulation) modelingmethod.A set of netname pairs representing bridging faultsites were extracted from layout and used for each faultmodeling method.Results show that pattern generationshould be driven by the most accurate modeling methodwhen pursuing 100% bridging coverage, since lessaccurate methods will not necessarily converge to a highquality result.