Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Path-delay-fault testability properties of multiplexor-based networks
Integration, the VLSI Journal
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
Towards One-Pass Synthesis
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be formulated in terms of symbolic BDD operations. By this, test pattern generation can be carried out in polynomial time. A technique to improve testability is presented. Experimental results show that a complete classification can be carried out very efficiently.