Path-delay-fault testability properties of multiplexor-based networks

Precomputation-based sequential logic optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Fast exact minimization of BDDs

DAC '98 Proceedings of the 35th annual Design Automation Conference

Minimization of free BDDs

Integration, the VLSI Journal

MuTaTe: an efficient design for testability technique for multiplexor based circuits

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Optimization of combinational and sequential logic circuits for low power using precomputation

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Decision Diagrams in Synthesis - Algorithms, Applications and Extensions

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Bridging fault testability of BDD circuits

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A genetic algorithm for the construction of small and highly testable OKFDD-circuits

GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation