A study of permutation crossover operators on the traveling salesman problem
Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application
Path-delay-fault testability properties of multiplexor-based networks
Integration, the VLSI Journal
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms Plus Data Structures Equals Evolution Programs
Genetic Algorithms Plus Data Structures Equals Evolution Programs
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Dynamic minimization of OKFDDs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
AllelesLociand the Traveling Salesman Problem
Proceedings of the 1st International Conference on Genetic Algorithms
Scheduling Problems and Traveling Salesmen: The Genetic Edge Recombination Operator
Proceedings of the 3rd International Conference on Genetic Algorithms
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
A Genetic Algorithm for Channel Routing Problem
Proceedings of the 5th International Conference on Genetic Algorithms
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
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A Genetic Algorithm (GA) is applied to derive circuits that combine area efficiency and testability. These circuits are obtained from Ordered Kronecker Functional Decision Diagrams (OKFDDs). In "Becker and Drechsler (1995)" a heuristic approach has been presented. In this paper we show how these results can further be improved by GAs. Finally, we apply our minimization algorithm to technology mapping for FPGAs. We present experimental results to show the efficiency of our approach.