Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping
EURO-DAC '94 Proceedings of the conference on European design automation
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On the Expressive Power of OKFDDs
Formal Methods in System Design
Parallel breadth-first BDD construction
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
A graph-based synthesis algorithm for AND/XOR networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
Efficient manipulation algorithms for linearly transformed BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Non-Abelian Groups in Optimization of Decision Diagrams Representations of Discrete Functions
Formal Methods in System Design
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Ordered binary decision diagrams
Logic Synthesis and Verification
Data structures for Boolean functions
Computational Discrete Mathematics
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division
Formal Methods in System Design
The K*BMD: A Verification Data Structure
IEEE Design & Test
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Lower bounds for linearly transformed OBDDs and FBDDs
Journal of Computer and System Sciences
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
Information and Computation - Special issue: LICS'97
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
EDTC '95 Proceedings of the 1995 European conference on Design and Test
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams
EDTC '95 Proceedings of the 1995 European conference on Design and Test
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A study of composition schemes for mixed apply/compose based construction of ROBDDs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A genetic algorithm for decomposition type choice in OKFDDs
INBS '95 Proceedings of the First International Symposium on Intelligence in Neural and Biological Systems (INBS'95)
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A genetic algorithm for the construction of small and highly testable OKFDD-circuits
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
Interactive cost configuration over decision diagrams
Journal of Artificial Intelligence Research
Efficient gröbner basis reductions for formal verification of galois field multipliers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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