Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
On the effect of local changes in the variable ordering of ordered decision diagrams
Information Processing Letters
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
The K*BMD: A Verification Data Structure
IEEE Design & Test
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Word-Level Decision Diagrams (WLLDs), like *BMDs or K*BMDs, have been introduced to overcome the limitations of Binary Decision Diagrams (BDDs), which are the state-of-the-art data structure to represent and manipulate Boolean functions. However, the size of these graph types largely depends on the variable ordering, i.e. it may vary from linear to exponential. In the meantime, dynamic approaches to find a good variable ordering are also known for WLDDs. In this paper, we show how these approaches can be accelerated significantly using a combination of a lower bound computation and synthesis operations. In the experiments it turned out that by this technique, the runtime for dynamic minimization can be reduced by more than 40% on average without loss of quality.