Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Using BDDs to verify multipliers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Model checking large software specifications
SIGSOFT '96 Proceedings of the 4th ACM SIGSOFT symposium on Foundations of software engineering
Word level model checking—avoiding the Pentium FDIV error
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Bit-level analysis of an SRT divider circuit
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VERILAT: verification using logic augmentation and transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Compilation of optimized OBDD-algorithms
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Verifying systems with integer constraints and Boolean predicates: a composite approach
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid techniques for fast functional simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Polynomial methods for component matching and verification
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The Theory of Zero-Suppressed BDDs and the Number of Knight‘s Tours
Formal Methods in System Design
A Method of Formal Verification of Cryptographic Circuits
Journal of Electronic Testing: Theory and Applications
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verifying imprecisely working arithmetic circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An efficient filter-based approach for combinational verification
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Polynomial methods for allocating complex components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Prove that a faulty multiplier is faulty!?
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Composite model-checking: verification with type-specific symbolic representations
ACM Transactions on Software Engineering and Methodology (TOSEM)
Abstraction of word-level linear arithmetic functions from bit-level component descriptions
Proceedings of the conference on Design, automation and test in Europe
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Equivalence checking of integer multipliers
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Polynomial circuit models for component matching in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Ordered binary decision diagrams
Logic Synthesis and Verification
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Linear Models of Circuits Based on the Multivalued Components
Automation and Remote Control
On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division
Formal Methods in System Design
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Induction-based gate-level verification of multipliers
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Modular Verification of SRT Division
Formal Methods in System Design
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
An Algebraic Approach to Formal Verification of Microprocessors
Journal of Electronic Testing: Theory and Applications
The K*BMD: A Verification Data Structure
IEEE Design & Test
Model Checking Large Software Specifications
IEEE Transactions on Software Engineering
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
Extracting gate-level networks from simulation tables
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Bisimulation Algorithms for Stochastic Process Algebras and Their BDD-Based Implementation
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Information and Computation - Special issue: LICS'97
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Probabilistic Bottom-Up RTL Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
A tutorial introduction to symbolic model checking
Logic for concurrency and synchronisation
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Automation and Remote Control
Representation of Logical Circuits by Linear Decision Diagrams with Extension to Nanostructures
Automation and Remote Control
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Application of Wu's method to symbolic model checking
Proceedings of the 2005 international symposium on Symbolic and algebraic computation
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
Secure function evaluation with ordered binary decision diagrams
Proceedings of the 13th ACM conference on Computer and communications security
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
AusDM '07 Proceedings of the sixth Australasian conference on Data mining and analytics - Volume 70
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
Arithmetic Circuit Verification Based on Symbolic Computer Algebra
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
XML Framework for Various Types of Decision Diagrams for Discrete Functions
IEICE - Transactions on Information and Systems
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modelling of complex systems given as a mealy machine with linear decision diagrams
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartII
Construction of efficient BDDs for bounded arithmetic constraints
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Interactive cost configuration over decision diagrams
Journal of Artificial Intelligence Research
On the BDD of a random boolean function
ASIAN'04 Proceedings of the 9th Asian Computing Science conference on Advances in Computer Science: dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday
VSOP (valued-sum-of-products) calculator for knowledge processing based on zero-suppressed BDDs
Proceedings of the 2005 international conference on Federation over the Web
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
Algebraic approach to arithmetic design verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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