Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A computational logic handbook
A computational logic handbook
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Cycle-based simulation with decision diagrams
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
dibSIM: a parallel functional logic simulator allowing dynamic load balancing
Proceedings of the conference on Design, automation and test in Europe
Model Checking of Safety Properties
Formal Methods in System Design
Model Checking of Safety Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Generalized cofactoring for logic function evaluation
Proceedings of the 40th annual Design Automation Conference
Using conjugate symmetries to enhance gate-level simulations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal Methods in System Design
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W e implement and experiment with techniques for the functional simulation of very large digital systems. We consider techniques that are a hybrid of classical compiled code simulation and recent branching program based simulation in order to resolve memory performance problems inherent to BDD based cycle simulation. Specifically, predefined functional units (“macros”) are extracted from the circuit and evaluated directly instead of building BDDs for them. The functionality of those macros, such as multipliers, filters, etc., can in turn be verified by simulation of their gate-level implementations respectively or by formal verification techniques. Our results demonstrate that this approach leads to considerably faster simulation.