Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
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ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
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ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
Modular construction of model partitioning processes for parallel logic simulation
International Journal of Computational Science and Engineering
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SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
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IEA/AIE'07 Proceedings of the 20th international conference on Industrial, engineering, and other applications of applied intelligent systems
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In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.