Modular construction of model partitioning processes for parallel logic simulation

Authors:
Klaus Hering;Gudula Runger;Sven Trautmann
Affiliations:
Department of Computer Science, Leipzig University of Applied Sciences, 04251 Leipzig, Germany.;Department of Computer Science, Chemnitz University of Technology, 09111 Chemnitz, Germany.;Department of Computer Science, Chemnitz University of Technology, 09111 Chemnitz, Germany
Venue:
International Journal of Computational Science and Engineering
Year:
2005

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Abstract

Logic simulation of complex VLSI models is very time consuming.Simulation speed can be increased by model partitioning andassigning the resulting parts to simulator instances whichcooperate over a loosely coupled system. We have developed adistributed framework, parallelMAP, that implements a hierarchicalmodel partitioning strategy. It can serve both as productionenvironment in VLSI design and as an experimental test bed foralgorithm development. In this paper, we describe the possibilitiesthat parallelMAP offers for the modular construction ofpartitioning processes, starting from basic sequential and parallelmodules. Experimental experiences refer to IBM processor modelscomprising from 1.5 x 105 to 2.5 x 106elements at gate level.