Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Corolla based circuit partitioning and resynthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Dynamic load balancing of a multi-cluster simulator on a network of workstations
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Spectral partitioning: the more eigenvectors, the better
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On implementation choices for iterative improvement partitioning algorithms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
New algorithms for min-cut replication in partitioned circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Linear decomposition algorithm for VLSI design applications
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A new system partitioning method under performance and physical constraints for multi-chip modules
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A robust min-cut improvement algorithm based on dynamic look-ahead weighting
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A new K-way partitioning approach for multiple types of FPGAs
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Delay optimal partitioning targeting low power VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New spectral linear placement and clustering approach
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance-driven partitioning using retiming and replication
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Three-phase chip planning — an improved top-down chip planning strategy
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
A Fast and Robust Network Bisection Algorithm
IEEE Transactions on Computers
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Circuit clustering for delay minimization under area and pin constraints
EDTC '95 Proceedings of the 1995 European conference on Design and Test
When clusters meet partitions: new density-based methods for circuit decomposition
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming.
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Optimum clustering for delay minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cut replication in partitioned networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit clustering using a stochastic flow injection method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization by iterative improvement: an experimental evaluation on two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Local ratio cut and set covering partitioning for huge logic emulation systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the acceleration of flow-oriented circuit clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiway partitioning via geometric embeddings, orderings, and dynamic programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A hierarchy-driven FPGA partitioning method
DAC '97 Proceedings of the 34th annual Design Automation Conference
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A three-step approach to the functional partitioning of large behavioral processes
Proceedings of the 11th international symposium on System synthesis
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Target architecture oriented high-level synthesis for multi-FPGA based emulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
A Parallel LCC Simulation System
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Comparison of Functional and Structural Partitioning
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Recursive bi-partitioning of netlists for large number of partitions
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
IEEE Transactions on Computers
SAT-based optimal hypergraph partitioning with replication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A PROBE-Based Heuristic for Graph Partitioning
IEEE Transactions on Computers
Modular construction of model partitioning processes for parallel logic simulation
International Journal of Computational Science and Engineering
Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
Wirelength minimization in partitioning and floorplanning using evolutionary algorithms
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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