Statecharts: A visual formalism for complex systems
Science of Computer Programming
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Introduction to algorithms
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Experience with image compression chip design using unified system construction tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Communicating sequential processes
Communications of the ACM
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
SLIF: a specification-level intermediate format for system design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
An Object-Oriented Communication Library for Hardware-Software CoDesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Hardware/Software Partitioning with Iterative Improvement Heuristics
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A methodology for control-dominated systems codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Min-cut replication in partitioned networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SpecCharts: a VHDL front-end for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Target architecture oriented high-level synthesis for multi-FPGA based emulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Partitioning sequential programs for CAD using a three-step approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
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Incorporating functional partitioning into a synthesis methodology leads to several important advantages. In functional partitioning, we first partition a functional specification into smaller subspecifications and then synthesize structure for each, in contrast to the current approach of first synthesizing structure for the entire specification and then partitioning that structure. One advantage is the improvement in I/O performance and package count, when partitioning among hardware blocks with size and I/O constraints, such as FPGAs or blocks within an ASIC. A second advantage is reduction in synthesis runtimes. We describe these important advantages, concluding that further research on functional partitioning can lead to inproved results from synthesis environments.