Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Manifestations of heterogeneity in hardware/software co-design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Software synthesis for DSP using Ptolemy
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
IEEE Transactions on Parallel and Distributed Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approach to interface synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Hardware/software partitioning of VHDL system specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
A codesign experiment in acoustic echo cancellation: GMDFα
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combining multiple models of computation for scheduling and allocation
Proceedings of the 6th international workshop on Hardware/software codesign
A path analysis based partitioning for time constrained embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A three-step approach to the functional partitioning of large behavioral processes
Proceedings of the 11th international symposium on System synthesis
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
On-line fault detection in a hardware/software co-design environment: system partitioning
Proceedings of the 14th international symposium on Systems synthesis
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Readings in hardware/software co-design
A path-based technique for estimating hardware runtime in HW/SW-Cosynthesis
Readings in hardware/software co-design
Incremental hardware estimation during hardware/software functional partitioning
Readings in hardware/software co-design
Partitioning sequential programs for CAD using a three-step approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Model for the Coanalysis of Hardware and Software Architectures
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A generic multi-unit architecture for codesign methodologies
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An Approach to Mixed Systems Co-Synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Aspects of system modelling in Hardware/Software partitioning
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Rapid Synthesis of Multi-Chip Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Hardware/Software Partitioning with Iterative Improvement Heuristics
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Hardware/Software Partitioning for Telecommunications Systems
COMPSAC '96 Proceedings of the 20th Conference on Computer Software and Applications
ACM Transactions on Embedded Computing Systems (TECS)
Efficient search space exploration for HW-SW partitioning
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Hardware/Software Co-Design Methodology for Design of Embedded Systems
Integrated Computer-Aided Engineering
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
Hardware/software partitioning with multi-version implementation exploration
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Low power asynchronous circuit back-end design flow
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An algorithm for the constrained hardware/software partitioning (assignment and scheduling) problem is presented. The key feature of the algorithm is the adaptive objective mechanism governed by the combination of global and local measures. As hardware area minimization and latency constraints present contradictory objectives, a global time-criticality (GC) measure selects an objective function in accordance with feasibility. In addition to global consideration, local characteristics of the nodes are emphasized by classifying nodes into local phase (LP) types. A local phase 1 node (extremity) has an obvious preference for an implementation on the basis of its arealtime requirements. A local phase 2 node (repeller) is a repeller to an implementation on the basis of relative preferences of other nodes. At each iteration, the global and local criteria are superimposed by a thresh-old mechanism so as to determine the best implementation. The algorithm has quadratic complexity in the number of nodes and has shown promising behavior on the examples tested.