Petri nets: an introduction
LUCID, the dataflow programming language
LUCID, the dataflow programming language
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Statecharts: A visual formalism for complex systems
Science of Computer Programming
Communications of the ACM
Communication and concurrency
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The definition of Standard ML
STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
TDFL: a task-level dataflow language
Journal of Parallel and Distributed Computing - Special issue: software tools for parallel programming and visualization
Automata for modeling real-time systems
Proceedings of the seventeenth international colloquium on Automata, languages and programming
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Synthesis of application-specific multiprocessor architectures
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
An introduction to functional programming systems using Haskell
An introduction to functional programming systems using Haskell
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Trace algebra for automatic verification of real-time concurrent systems
Trace algebra for automatic verification of real-time concurrent systems
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A stubborn attack on state explosion
Formal Methods in System Design - Special issue on computer-aided verification: special methods I
On the power of bounded concurrency I: finite automata
Journal of the ACM (JACM)
Logic synthesis
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
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DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
System design methodologies: aiming at the 100 h design cycle
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounded scheduling of process networks
Bounded scheduling of process networks
Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Heterogeneous Simulation—Mixing Discrete-Event Models with Dataflow
Journal of VLSI Signal Processing Systems - Special issue on the rapid prototyping of application specific signal processors (RASSP) program
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A partitioning algorithm for system-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computability of Recursive Functions
Journal of the ACM (JACM)
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Communicating sequential processes
Communications of the ACM
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Petri Net Theory and the Modeling of Systems
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Denotational Semantics: The Scott-Strachey Approach to Programming Language Theory
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Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Constructing Predictable Real Time Systems
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High-Level VLSI Synthesis
Introduction To Automata Theory, Languages, And Computation
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Telecommunications Systems Engineering Using SDL
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A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Scheduling for Reactive Real-Time Systems
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Declustering: A New Multiprocessor Scheduling Technique
IEEE Transactions on Parallel and Distributed Systems
Traces, Histories, Graphs: Instances of a Process Monoid
Proceedings of the Mathematical Foundations of Computer Science 1984
Using PO Methods for Verfying Behavioural Equivalences
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A Comparison of Statecharts Variants
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Specification and verification of concurrent systems in CESAR
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Transport-Triggering versus Operation-Triggering
CC '94 Proceedings of the 5th International Conference on Compiler Construction
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Timing Verification by Successive Approximation
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
A Verification Strategy for Timing-Constrained Systems
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Suspension Automata: A Decidable Class of Hybrid Automata
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Logics and Models of Real Time: A Survey
Proceedings of the Real-Time: Theory in Practice, REX Workshop
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Proceedings of the Real-Time: Theory in Practice, REX Workshop
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
A methodology for control-dominated systems codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
COSMOS: a codesign approach for communicating systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Configuration-level hardware/software partitioning for real-time embedded systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Constrained software generation for hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Design flow for hardware/software cosynthesis of a video compression system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Flexible modeling environment for embedded systems design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Towards a theory for hardware/software codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Towards a declarative framework for hardware-software codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Hardware/software selected cycle solution
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CASTLE: an interactive environment for HW-SW Co-Design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Towards provably correct hardware/software partitioning using occam
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Analysis and synthesis of concurrent digital circuits using control-flow expressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the design of reactive real-time embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems. We review the variety of approaches to these problems that have been taken.