Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
Don't care-based BDD minimization for embedded software
DAC '98 Proceedings of the 35th annual Design Automation Conference
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Efficient canonical form for boolean matching of complex functions in large libraries
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Knowledge discovery with second-order relations
Knowledge and Information Systems
On the Complexity and Inapproximability of Shortest Implicant Problems
ICAL '99 Proceedings of the 26th International Colloquium on Automata, Languages and Programming
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hardness of Approximating Minimization Problems
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Restructuring decision tables for elucidation of knowledge
Data & Knowledge Engineering
A synthesis oriented omniscient manual editor
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Utilizing don't care states in SAT-based bounded sequential problems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Factoring boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Synthesis of multi-level dual reed-muller expressions
NANOTECHNOLOGY'09 Proceedings of the 1st WSEAS international conference on Nanotechnology
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Factoring Boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The complexity of Boolean formula minimization
Journal of Computer and System Sciences
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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