Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Logic synthesis
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Timing analysis and optimization of a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A theoretical probabilistic simulation framework for dynamic power estimation
Proceedings of the International Conference on Computer-Aided Design
Simultaneous clock and data gate sizing algorithm with common global objective
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. This has a significant impact on the delay, power dissipation, and area of the final circuit. The gate sizing methods previously proposed suffer from problems that make them difficult to apply on real-life large circuits. This paper presents GS, a gate sizing based general purpose optimization algorithm, which has the following characteristics: it can optimize the power or/and area under some delay constraints, or the delay under some power or/and area constraints; it can take into account user defined or library dependent design rules; as opposed to greedy approaches, it addresses non-linear, non-unimodal, constrained optimization, in order to handle complex cost models (e.g., delay and power); it can be applied on large circuits within a reasonable CPU time, e.g., 10000 nodes in 2 hours for power optimization under delay constraints.