Area-delay optimization of programmable logic arrays
Proceedings of the fourth MIT conference on Advanced research in VLSI
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An efficient compactor for 45° layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An electrical optimizer that considers physical layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing Models for MOS Circuits
Timing Models for MOS Circuits
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
PERFLEX: a performance driven module generator
EURO-DAC '92 Proceedings of the conference on European design automation
P.SIZE: a sizing aid for optimized designs
EURO-DAC '92 Proceedings of the conference on European design automation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An iterative gate sizing approach with accurate delay evaluation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimization of custom MOS circuits by transistor sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
MINFLOTRANSIT: min-cost flow based transistor sizing tool
Proceedings of the 37th Annual Design Automation Conference
Transistor sizing of energy-delay--efficient circuits
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Speed indicators for circuit optimization
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.