Generating incremental VLSI compaction spacing constraints
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Nutcracker: an efficient and intelligent channel spacer
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Improving virtual-grid compaction through grouping
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
A fully automatic hierarchical compactor
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
Ic layout generation and compaction using mathematical optimization
Ic layout generation and compaction using mathematical optimization
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Technology tracking of non manhattan VLSI layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Layout synthesis of MOS digital cells
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout compaction with attractive and repulsive constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A hierarchy preserving hierarchical compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A new approach to hierarchical adaptation using sequence-control based on cell interactions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
VLSI layout compaction using radix priority search trees
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hierarchical pitchmatching compaction using minimum design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimal graph constraint reduction for symbolic layout compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
Developing a concurrent methodology for standard-cell library generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Technology retargeting for IC layout
DAC '97 Proceedings of the 34th annual Design Automation Conference
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
Rapid Prototyping of High-Speed Communications Chips
IEEE Design & Test
Optimal Joining of Compacted Cells
IEEE Transactions on Computers
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Automatic process migration of datapath hard IP libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Lithography-aware layout compaction
Proceedings of the great lakes symposium on VLSI
Automatic design rule correction in presence of multiple grids and track patterns
Proceedings of the 50th Annual Design Automation Conference
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Symbolic layout and compaction is reaching a mature status. This is demonstrated, in part, by the recent or imminent introductions of a number of commercial symbolic layout and compaction systems. The two most frequently used symbolic layout compaction approaches, constraint graph compaction and virtual grid compaction, are reviewed in this paper. The current status of these two approaches is presented by looking at the results of the ICCD87 compaction benchmark session.