A compaction method for full chip VLSI layouts
DAC '93 Proceedings of the 30th international Design Automation Conference
Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A methodology for concurrent fabrication process/cell library optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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This paper describes the development of a concurrentmethodology for standard cell library generation. Use of anovel physical design automation method enables a high degreeof concurrency among process, circuit, and layout development.In addition to reducing overall time-to-market, the newmethod allows optimization to occur simultaneously across thecircuit, layout, and process design spaces. The result is librarieswith improved density, circuit performance, and process yield.