An O(n1.5logn) 1-d compaction algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Topology-driven cell layout migration with collinear constraints
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A technology-agnostic simulation environment (TASE) for iterative custom ic design across processes
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few microprocessor companies. The reusability of datapath intellectual property (IP) libraries is largely limited by their dependence on process technology. Layout migration tools today, which are based on layout compaction developed decades ago, cannot cope with the challenges involved. In this paper, we present a comprehensive datapath IP development framework that can perform process migration by accommodating advanced circuit considerations, layout architecture and transistor sizing, in addition to design rule satisfaction. We demonstrate the effectiveness of the framework by migrating the Berkeley low power library, originally developed for 1.2um MOSIS process, into TSMC 0.25um and 0.18um technology.