A technology-agnostic simulation environment (TASE) for iterative custom ic design across processes

Authors:
Satyanand Nalam;Mudit Bhargava;Kyle Ringgenberg;Ken Mai;Benton H. Calhoun
Affiliations:
University of Virgnia, Carnegie Mellon University;University of Virgnia, Carnegie Mellon University;University of Virgnia, Carnegie Mellon University;University of Virgnia, Carnegie Mellon University;University of Virgnia, Carnegie Mellon University
Venue:
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Year:
2009

Citing 4
Cited 1

A Framework for Designing Reusable Analog Circuits

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Automatic process migration of datapath hard IP libraries

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
New Generation of Predictive Technology Model for Sub-45nm Design Exploration

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Chameleon ART: a non-optimization based analog design migration framework

Proceedings of the 43rd annual Design Automation Conference

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers

Proceedings of the 47th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A designer's intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designer's knowledge and separate it from the technologyspecific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm.