Algorithms for routing and testing routability of planar VLSI layouts
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Process independent constraint graph compaction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cell-based hierarchical pitchmatching compaction using minimal LP
DAC '93 Proceedings of the 30th international Design Automation Conference
A compaction method for full chip VLSI layouts
DAC '93 Proceedings of the 30th international Design Automation Conference
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
The edge-based design rule model revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph-optimization techniques for IC layout and compaction
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic process migration of datapath hard IP libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
TEG: a new post-layout optimization method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Calligrapher: a new layout-migration engine for hard intellectual property libraries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditional layout migration focuses on area minimization, thus suffered wire distortion, which caused loss of layout topology. A migrated layout inheriting original topology owns original design intention and predictable property, such as wire length which determines the path delay importantly. This work presents a new rectangular topological layout to preserve layout topology and combine its flexibility of handling wires with traditional scan-line based compaction algorithm for area minimization. The proposed migration flow contains devices and wires extraction, topological layout construction, unidirectional compression combining scanline algorithm with collinear equation solver, and wire restoration. Experimental results show that cell topology is well preserved, and a several times runtime speedup is achieved as compared with recent migration research based on ILP (integer linear programming) formulation.