Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
Technology migration techniques for simplified layouts with restrictive design rules
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous layout migration and decomposition for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Topology-driven cell layout migration with collinear constraints
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A framework for double patterning-enabled design
Proceedings of the International Conference on Computer-Aided Design
Planar CMOS to multi-gate layout conversion for maximal fin utilization
Integration, the VLSI Journal
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Modern systems-on-a-chip depend heavily on hard intellectual properties, such as standard cell and datapath libraries. As the foundries accelerate their update of advanced processes with increasingly complex design rules, and the libraries grow in flexibility and size, the cost of library development becomes prohibitively high. Automated layout-migration techniques used today, which are based on layout compaction developed a decade ago, corrupt advanced design considerations by honoring only design rules, and cannot cope with some of the new challenges involved. In this paper, we present a new integer linear programming (ILP)-based layout-migration engine, called calligrapher, and make the following contributions. First, we extend the recently proposed minimum perturbation (MP) metric designed to retain original layout design intentions, while overcoming its shortcoming of biased treatment of layout objects. Second, we propose a new design-rule-constraint algorithm, and prove its linear complexity for the number of constraints generated. Compared with what has been achieved in the literature, the proposed algorithm can significantly reduce the ILP solver time by limiting the constraint size. Third, we propose an iterative migration framework based on the concept of soft constraint. With this framework, two-dimensional compaction quality can be achieved with a runtime comparable to one-dimensional compaction. We demonstrate the effectiveness of calligrapher by migrating the Berkeley low-power libraries, originally developed for the 1.2-μm MOSIS process, into TSMC 0.25- and 0.18-μm technologies. We show that even for a very compact layout, our metric and the MP metric can make a difference by as much as 20%-45%. We also show that our iterative algorithm can improve the area by 10% on average compared to the traditional technique using the MP metric, and inflates the area by merely 7.5% compared to the traditional technique using minimum-area metric.