A new polynomial-time algorithm for linear programming
Combinatorica
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Simultaneous layout migration and decomposition for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Layout decomposition approaches for double patterning lithography
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and lossless graph division method for layout decomposition using SPQR-tree
Proceedings of the International Conference on Computer-Aided Design
Native-conflict-aware wire perturbation for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
New placement prediction and mitigation techniques for local routing congestion
Proceedings of the International Conference on Computer-Aided Design
Calligrapher: a new layout-migration engine for hard intellectual property libraries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for the early exploration of design rules for multiple-patterning technologies
Proceedings of the International Conference on Computer-Aided Design
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
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While the next generation of lithography systems is still under development, extending optical lithography using double patterning (DP) is the only solution to continue technology scaling. The biggest technical challenge of DP is the presence of mask-assignment conflicts in dense layers. In this paper, we propose a framework for DP conflict removal for standard cells. First, we offer an O(n) algorithm for mask assignment (up to 200x faster than the ILP-based approach) that guarantees a conflict-free solution if one exists. We then formulate the problem of conflict removal as a linear program (LP), which permits an extremely fast run-time (less than 10 seconds in real time for typical cells). The framework removes DP conflicts and legalizes the layout across all layers simultaneously while minimizing layout perturbation. For cells from a commercial 22nm library designed without any DP awareness, our method usually removes all DP conflicts without any area increase; for some complex cells, the method still removes all conflicts with a modest 6.7% average increase in area. The method is more general, however, and can also be applied for macro layouts and the interconnect layers in complete designs as we demonstrate in the paper.