Computing Orthogonal Drawings with the Minimum Number of Bends
IEEE Transactions on Computers
The LEDA Platform of Combinatorial and Geometric Computing
ICALP '97 Proceedings of the 24th International Colloquium on Automata, Languages and Programming
A Linear Time Implementation of SPQR-Trees
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
Bright-Field AAPSM Conflict Detection and Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast and efficient phase conflict detection and correction in standard-cell layouts
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Nanolithography and CAD challenges for 32nm/22nm and beyond
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Spectrum
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for double patterning-enabled design
Proceedings of the International Conference on Computer-Aided Design
Scalable genome scaffolding using integer linear programming
Proceedings of the ACM Conference on Bioinformatics, Computational Biology and Biomedicine
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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Double patterning lithography is the most likely solution for 32nm and below process nodes due to its cost effectiveness. To enable this technique, layout decomposition is applied to split a layout into two non-conflicting patterns. Nevertheless, this problem is NP-hard in general, especially for layouts with random logic. Thus, high quality results are hard to be achieved in reasonable time. Previously, several graph partitioning techniques have been presented in order to speed up the process, with the tradeoff of the quality of results (QoR). We propose a graph division method that does not have this deficiency. First, we start with a conflict graph derived from a layout. Based on a data structure named SPQR-tree, the graph is divided into its triconnected components in linear time. The solutions of these components are then combined in a way that no QoR is lost. Thus, we call this method a "lossless" method. Experimental results show that the proposed method can achieve 5X speedup without sacrificing any QoR.