Bright-Field AAPSM Conflict Detection and Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast and efficient phase conflict detection and correction in standard-cell layouts
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th international workshop on System level interconnect prediction
Double patterning lithography friendly detailed routing with redundant via consideration
Proceedings of the 46th Annual Design Automation Conference
Simultaneous layout migration and decomposition for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A mask double patterning technique using litho simulation by wavelet transform
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Layout decomposition approaches for double patterning lithography
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is double patterning lithography and its impact on nanometer design?
ACM SIGDA Newsletter
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mask cost reduction with circuit performance consideration for self-aligned double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Post-routing layer assignment for double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Proceedings of the 48th Design Automation Conference
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Template-mask design methodology for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Fast and lossless graph division method for layout decomposition using SPQR-tree
Proceedings of the International Conference on Computer-Aided Design
Native-conflict-aware wire perturbation for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
A polynomial time exact algorithm for self-aligned double patterning layout decomposition
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
Post-routing layer assignment for double patterning with timing critical paths consideration
Integration, the VLSI Journal
A polynomial time triple patterning algorithm for cell based row-structure layout
Proceedings of the International Conference on Computer-Aided Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
An efficient layout decomposition approach for triple patterning lithography
Proceedings of the 50th Annual Design Automation Conference
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system
Proceedings of the 50th Annual Design Automation Conference
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography
Proceedings of the 50th Annual Design Automation Conference
Double-patterning friendly grid-based detailed routing with online conflict resolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Constrained pattern assignment for standard cell based triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 2014 on International symposium on physical design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated testcases in 45nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.