Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
TRIAD: a triple patterning lithography aware detailed router
Proceedings of the International Conference on Computer-Aided Design
Double-patterning friendly grid-based detailed routing with online conflict resolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Double patterning technology (DPT) is emerging as the dominant technology to achieve the 32-nm node and beyond. Two challenges faced by DPT are layout decomposition and overlay error. To handle the challenges, some effort has been made to consider DPT during detailed routing. In this paper, we propose two enhancing techniques for DPT-friendly detailed routing: lazy color decision and last conflict segment recording. Experiments show that our techniques are able to reduce the number of stitches by 15~20% with 4% increase in running time.