Layer Assignment Problem for Three-Layer Routing
IEEE Transactions on Computers
Note: MAX-CUT and MAX-BISECTION are NP-hard on unit disk graphs
Theoretical Computer Science
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning lithography friendly detailed routing with redundant via consideration
Proceedings of the 46th Annual Design Automation Conference
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
An efficient approach to multilayer layer assignment with an application to via minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
Post-routing layer assignment for double patterning with timing critical paths consideration
Integration, the VLSI Journal
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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Double patterning lithography, where one-layer layout is decomposed into two masks, is believed to be inevitable for 32nm technology node of the ITRS roadmap. However, post-routing layer assignment, which decides the layout pattern on each layer, thus having great impact on double patterning related parameters, has not been explored in the merit of double patterning. In this paper, we propose a post-routing layer assignment algorithm for double patterning optimization. Our solution consists of three major phases: multi-layer assignment, single-layer double patterning, and via reduction. For phase one and three, multi-layer graph is constructed and dynamic programming is employed to solve optimization problem on this graph. In the second phase, single-layer double patterning is proved NP-hard and existing algorithm is implemented to optimize single layer double patterning problem. The proposed method is tested on CBL (Collaborative Benchmarking Laboratory) benchmarks and shows great performance. In comparison with single-layer double patterning, our method achieves 73% and 27% average reduction for unresolvable conflicts and stitches respectively, with only 9% increase of via number. When double patterning is constrained on only the bottom two metal layers as in current technology, these numbers become 62%, 8% and 0.42%.