Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
What is double patterning lithography and its impact on nanometer design?
ACM SIGDA Newsletter
Post-routing layer assignment for double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Template-mask design methodology for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Post-routing layer assignment for double patterning with timing critical paths consideration
Integration, the VLSI Journal
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achieve high quality solution for DPL-unfriendly designs, due to complex 2D patterns in lower metal layers. Therefore, DPL-friendliness is needed at routing stage [3]. Another key yield improvement technique is redundant via insertion [4] [5]. However, this would increase the complexity in DPL-compliance. To make designs manufacturable in DPL, we should not insert a redundant via if it results in coloring conflict. This paper is the first work to consider DPL and redundant via together. We have developed two algorithms, post-routing DPL-aware insertion and DPL-friendly routing with redundant via consideration to take into account redundant via DPL-compliance. Experimental results show that, compared to a DPL-aware optimization flow without redundant via consideration, we can improve insertion rate by 43% while still achieving zero coloring conflicts. Moreover, we can reduce the number of vias and stitches by 9% and 17% respectively.