Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning lithography friendly detailed routing with redundant via consideration
Proceedings of the 46th Annual Design Automation Conference
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
A mask double patterning technique using litho simulation by wavelet transform
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Layout decomposition approaches for double patterning lithography
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is double patterning lithography and its impact on nanometer design?
ACM SIGDA Newsletter
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mask cost reduction with circuit performance consideration for self-aligned double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Proceedings of the 48th Design Automation Conference
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
A statistical yield optimization framework for interconnect in double patterning lithography
Microelectronics Journal
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
A framework for double patterning-enabled design
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Native-conflict-aware wire perturbation for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient layout decomposition approach for triple patterning lithography
Proceedings of the 50th Annual Design Automation Conference
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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Double patterning lithography (DPL) is considered as a most likely solution for 32nm/22nm technology. In DPL, the layout patterns are decomposed into two masks (colors). Two features (polygons) have to be assigned opposite colors if their spacing is less than certain minimum coloring distance. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may be split into two parts to resolve the conflict but the resulting stitch causes yield loss due to overlay error and increases manufacturing cost. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose an algorithm to minimize the number of conflicts and stitches simultaneously. Our algorithm is based on grid layout model and integer linear programming. Two techniques, independent component computation and layout partition, are proposed to reduce runtime of the algorithm. The experimental results show that, compared with the two phase decomposition flow, the proposed algorithm reduces the conflicts significantly using less stitches under reasonable runtime.