Layout decomposition approaches for double patterning lithography

Authors:
Andrew B. Kahng;Chul-Hong Park;Xu Xu;Hailong Yao
Affiliations:
Departments of Computer Science and Engineering, and Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;Samsung Electronics Company, Seoul, Korea;Synopsys Inc., Mountain View, CA;Department of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Year:
2010

Citing 7
Cited 6

Improved algorithms for hypergraph bipartitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Bright-Field AAPSM Conflict Detection and Correction

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast and efficient phase conflict detection and correction in standard-cell layouts

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Layout decomposition for double patterning lithography

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization

Proceedings of the 2009 international symposium on Physical design

Exploration of VLSI CAD researches for early design rule evaluation

Proceedings of the 16th Asia and South Pacific Design Automation Conference
A framework for double patterning-enabled design

Proceedings of the International Conference on Computer-Aided Design
A novel layout decomposition algorithm for triple patterning lithography

Proceedings of the 49th Annual Design Automation Conference
TRIAD: a triple patterning lithography aware detailed router

Proceedings of the International Conference on Computer-Aided Design
Role of design in multiple patterning: technology development, design enablement and process control

Proceedings of the Conference on Design, Automation and Test in Europe
Fast and scalable parallel layout decomposition in double patterning lithography

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45nm testcases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.