Communications of the ACM
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-routing layer assignment for double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and lossless graph division method for layout decomposition using SPQR-tree
Proceedings of the International Conference on Computer-Aided Design
Native-conflict-aware wire perturbation for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Post-routing layer assignment for double patterning with timing critical paths consideration
Integration, the VLSI Journal
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Double patterning lithography-aware analog placement
Proceedings of the 50th Annual Design Automation Conference
Double-patterning friendly grid-based detailed routing with online conflict resolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
| Hi-index | 0.00 |
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain distance from each other on each layer onto two masks instead of one mask in traditional lithography. In this paper, we prove that the conflict graph used to model DPL conflicts in layout is a planar graph. Based on the planarity of the conflict graph, we propose a new face merging based framework which formulates DPL decomposition as a problem of pairing odd faces to simultaneously inimize the number of stitches generated and conflicts to eliminate. We employ partitioning and simplification techniques to reduce the problem size and use an O(n3) time maximum weighted matching algorithm to generate an optimal DPL decomposition.